Efficient canonic signed digit recoding

In this work novel-efficient implementations to convert a two’s complement binary number into its canonic signed digit (CSD) representation are presented. In these CSD recoding circuits two signals, H and K, functionally equivalent to two carries are described. They are computed in parallel reducing the critical path and they possess some properties that lead to a simplification of the algebraic expressions minimizing the overall hardware implementation. As a result, the proposed circuits are highly efficient in terms of speed and area in comparison with other counterpart previous architectures. Simulations of different configurations made over standard-cell implementations show an average reduction of about 55% in the delay and 29% in the area for a ripple-carry scheme, 47% in the delay and 17% the area in a carry look-ahead scheme, and 36% in the delay and 31% the area in a parallel prefix scheme.

► Two carry-like signals permit new efficient standard cell-based implementations.
► To convert a two’s complement binary number into its canonic signed digit representation.
► These signals are computed in parallel reducing the critical path and simplifying the algebraic expressions.
► Simulations highlight high efficiency in terms of speed and area in comparison with other previous counterpart architectures.