Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology

This paper deals with the design of a fractional PLL for wireless multi-standard applications. This circuit has been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. Five standards are covered by this structure: GSM (900 MHz), DCS (1.8 GHz), Bluetooth (2.45 GHz) and 802.11a (5.8 GHz). Based on multi-engine simulators, associated with a hierarchical models library, a virtual RF system platform, which allows designing complex SoCs, is also presented. The PLL, including digital and analogue parts, constitutes a very good benchmark to validate this platform.