Modelling of hot-carrier degradation and its application for analog design for reliability

An analytical CMOS transistor ageing model is presented and a new procedure that allows the extraction of its parameters are presented in this paper. Then, we show how this model can be used to forecast and understand the drifts of the main characteristics of a CMOS circuit. Further, we demonstrate that this model can also be used to help the analog designer to choose and/or modify a circuit in order to minimise the hot-carrier induced degradations. Finally, we use an ageing simulation tool realised in VHDL-AMS to validate the analytical study, and we present our first experimental results.