Power dissipation sources and possible control techniques in ultra deep submicron CMOS technologies

As technology scales down into the ultra deep-submicron (UDSM) region, the static power dissipations grow exponentially and become an increasingly dominant component of the total power dissipation in CMOS circuits. With increase in gate leakage current resulting from thinner gate oxides in UDSM and the problems associated with short channel effects, leakage power dissipation is becoming a huge factor challenging a continuous success of CMOS technology in the semiconductor industry. With strict limitations of maximum allowable power (the power being limited more by system level cooling and test constraints than packaging) of 2.8 W (in 2005) to 3 W (in 2020) for battery (low cost/handheld) operated devices as projected by the International Technology Roadmap for Semiconductors (ITRS) 2005, innovations in leakage control and management are urgently needed. This paper presents an overview of the sources of the power dissipation mechanisms in the UDSM technologies, and the device and circuit techniques to control them.