کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
542581 | 1450230 | 2016 | 7 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
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چکیده انگلیسی
This paper deals with multiobjective analog circuit optimization taking into consideration performance sensitivity vis-a-vis parameters' variations. It mainly considers improving computation time of the inloop optimization approaches by including sensitivity considerations in the Pareto front generation process, not as a constraint, but by involving it within the used metaheuristic evolution process. Different approaches are proposed and compared. NSGA-II metaheuristic is considered. The proposed sensitivity aware approaches are showcased via two analog circuits, namely, a second generation CMOS current conveyor and a CMOS voltage follower. We show that the proposed ideas considerably alleviate the long computation time of the process and improve the quality of the generated front, as well.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 55, September 2016, Pages 220-226
Journal: Integration, the VLSI Journal - Volume 55, September 2016, Pages 220-226
نویسندگان
O. Bellaaj Kchaou, A. Garbaya, M. Kotti, P. Pereira, M. Fakhfakh, M. Helena Fino,