Post-process die-level electromagnetic field analysis on microwave CMOS low-noise amplifier for first-pass silicon fabrication success

• Target is to avoid post-fabrication tuning or re-fabrication for discrepancy tuning.
• Die-level electromagnetic analysis for RF CMOS integrated circuits is studied.
• EM-simulated results are compared against the measured ones for 130-nm RF CMOS LNA.
• EM analysis showed higher correlation with characterization than conventional tools.

In this study, the die-level electromagnetic interaction between components and parasitic interconnection extraction are evaluated with the measurement results of a 0.13 μm radio-frequency CMOS low-noise amplifier (LNA). This work aims to achieve first-pass silicon fabrication success to avoid costly and time-consuming additional fabrications for optimization. To achieve this target, a full-wave 3D-planar electromagnetic (EM) solver called “Sonnet” is applied, and simplification techniques are introduced for complex circuits. The layout of a fabricated LNA chip was modeled and analyzed in an EM solution. The achieved scattering parameters and noise figure from the EM model are then compared with the measured results and those from a conventional RC parasitic extraction tool for evaluation. The simulated parameters, such as input and output return losses, power gain, reverse isolation, noise figure and noise resistance, as well as stability factor, exhibit excellent agreement with the results achieved from a characterized LNA chip. However, the post-layout optimization of LNA is based on a conventional RC parasitic extraction tool, which causes frequency-shifted measured results. The promising results confirm that the use of this method before fabrication significantly reduces the requirement of further re-fabrications for optimization and guarantees first-pass fabrication success for radio-frequency integrated circuits. This method has the feasibility of implementation for industrial application.