Cost-effective integration of an FN-programmed embedded flash memory into a 0.25 μm SiGe:C RF-BiCMOS technology

 This paper presents a process technology for cost-effective integration of low-power flash memories into a 0.25 μm, high performance SiGe:C RF-BiCMOS process. Only four additional lithographic steps are used on top of the baseline BiCMOS process, leading to in total 23 mask levels for the BiCMOS/embedded flash process. Uniform-channel Fowler–Nordheim programmable and erasable stacked-gate cells, suitable for medium density (∼Mbit) memories, are demonstrated. Peripheral high-voltage transistors, with >10 V breakdown voltage, are integrated without additional mask steps on top of the flash cell integration. The flash memory integration is modular and has negligible impact on the original CMOS and HBT device parameters.