Area-time efficient end-around inverted carry adders

Novel architectures for end-around inverted carry adders are proposed in this manuscript, which use a sparse carry computation unit for deriving only some of the carries in log2nlog2n prefix levels, while all the rest are computed in an extra one. When used for the design of modulo 2n+1 adders, the proposed designs offer significant area and power savings compared to earlier proposals, while maintaining a high operation speed.

► A new family of end-around inverted carry adders is proposed.
► Each member is based on a sparse parallel prefix carry computation unit.
► Some carries are computed in log2nlog2n levels, while the rest in an extra one.
► Significant area and power savings are offered, while a high speed is maintained.