Bus-driven floorplanning with bus pin assignment and deviation minimization

As the number of buses increase substantially in multi-core SoC designs, the bus planning problem has become the dominant factor in determining the performance and power consumption of SoC designs. To cope with the bus planning problem, it is desirable to consider this issue in early floorplanning stage. Recently, the bus-driven floorplanning problem has attracted much attention in the literature. However, current algorithms adopt an over-simplified formulation which ignores the orientation of the bus pin, the chip performance may be deteriorated. In this paper, we propose the bus-driven floorplanning algorithm that fully considers the impact of the bus pin. By fully utilizing the position and orientation of the bus pin, bus bendings are not restricted to occur at the module of the same bus, then more flexible bus shape is obtained. With more flexibility on the bus shape, the size of the solution space is increased and a better bus-driven floorplanning solution can be obtained. In conference version, compared with the bus-driven floorplanner [6], experimental results show that our algorithm performs better in runtime by 3.5×, bus wirelength by 1.4×, and deadspace by 1.2×, respectively. In this paper, we improve the algorithm in [11] to obtain better driver-load delay variation among all bus bits.

► We develop two algorithms to minimize the wirelength deviation of each bus.
► We conclude 150 deviation patterns which can be used to efficiently determine the wirelength deviation.
► We explore the diagonal connection between different modules to make bus shape more flexible.
► The modified graph coloring algorithm is developed to determine the layer of each bus such that no via is used at the bend of the diagonal bus.
► Two wirelength reduction algorithms are developed to improve total bus wirelength.