Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates

In this paper, a new design for low leakage and noise immune wide fan-in domino circuits is presented. The proposed technique uses the difference and the comparison between the leakage current of the OFF transistors and the switching current of the ON transistors of the pull down network to control the PMOS keeper transistor, yielding reduction of the contention between keeper transistor and the pull down network from which previously proposed techniques have suffered. Moreover, using the stacking effect, leakage current is reduced and the performance of the current mirror is improved. Results of simulation in high performance 16 nm predictive technology model (PTM) demonstrate that the proposed circuit exhibits about 39% less power consumption, and nearly 2.57 times improvement in noise immunity with a 41% die area overhead for a 64-bit OR gate compared to a standard domino circuit.

► A new leakage and noise tolerant domino logic circuit is proposed for wide gates.
► The keeper is controlled to decrease contention using current comparison.
► Using diode-footed transistor decreases leakage and increases noise immunity.
► A normalized figure of merit including die area, power, delay and UNG is defined.
► The proposed circuit is superior to existing designs especially for wide gates.