Statistical DOE–ILP based power–performance–process (P3) optimization of nano-CMOS SRAM

As technology continues to scale, maintaining important figures of merit of Static Random Access Memories (SRAMs), such as power dissipation and an acceptable Static Noise Margin (SNM), becomes increasingly challenging. In this paper, we address SRAM instability and power (leakage) dissipation in scaled-down technologies by presenting a novel design flow for simultaneous power minimization, performance maximization and process variation tolerance (P3) optimization of nano-CMOS circuits. The 45 and 32 nm technology node standard 6-Transistor (6T) and 8T SRAM cells are used as example circuits for demonstration of the effectiveness of the flow. Thereafter, the SRAM cell is subjected to a dual threshold voltage (dual-VTh) assignment based on a novel statistical Design of Experiments–Integer Linear Programming (DOE–ILP) approach. Experimental results show 61% leakage power reduction and 13% increase in the read SNM. In addition, process variation analysis of the optimized cell is conducted considering the variability effect in twelve device parameters. To the best of the authors' knowledge, this is the first study which makes use of statistical DOE–ILP for optimization of conflicting targets of stability and power in the presence of process variations in SRAMs.

► A novel design flow for SRAM power–performance–process optimization is presented.
► Design of 45 nm standard 6T and 8T SRAM cells is demonstrated.
► A DOE–ILP based optimization that achieves 61% power reduction is presented.
► Process variation analysis of the optimal SRAM with 12 parameters is demonstrated.
► The 32 nm technology node based 6T and 8T cell SRAM is investigated.