Design and design methods for unified multiplier and inverter and its application for HECC

This paper describes two novel architectures for a unified multiplier and inverter (UMI) in GF(2m): the UMI merges multiplier and inverter into one unified data-path. As such, the area of the data-path is reduced. We present two options for hyperelliptic curve cryptography (HECC) using UMIs: an FPGA-based high-performance implementation (Type-I) and an ASIC-based lightweight implementation (Type-II). The use of a UMI combined with affine coordinates brings a smaller data-path, smaller memory and faster scalar multiplication.Both implementations use curves defined by h(x)=x   and f(x)=x5+f3x3+x2+f0f(x)=x5+f3x3+x2+f0. The high throughput version uses 2316 slices and 2016 bits of block RAM on a Xilinx Virtex-II FPGA, and finishes one scalar multiplication in 311μs. The lightweight version uses only 14.5 kGates, and one scalar multiplication takes 450 ms.

► Two novel architectures for a unified multiplier and inverter in GF(2m).
► An FPGA-based HECC design finishes one scalar multiplication in 311μs.
► An ASIC HECC design uses only 14.5 kGates.