کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
542834 871588 2009 8 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Block flipping and white space distribution for wirelength minimization
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
Block flipping and white space distribution for wirelength minimization
چکیده انگلیسی

Floorplanning plays an important role in the physical design of very large scale integration (VLSI) circuits. Traditional floorplanners use heuristics to optimize a floorplan based on multiple objectives. Besides traditional floorplanning approaches, some post-floorplanning steps can be applied to consider block flipping, pin assignment and white space distribution to optimize the performance. If we can consider the above three optimizations simultaneously as a post-floorplanning step, the total wirelength can be further reduced without modifying the original floorplan topology. Experimental results show that our approach can handle these issues simultaneously and wirelength can be further improved with a small penalty in runtime. Thus, this approach is highly desirable to be incorporated into a floorplanner as a post-processing step for wirelength optimization.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 42, Issue 2, February 2009, Pages 246–253
نویسندگان
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