کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
542888 | 871592 | 2008 | 15 صفحه PDF | دانلود رایگان |
![عکس صفحه اول مقاله: High performance set associative translation lookaside buffers for low power microprocessors High performance set associative translation lookaside buffers for low power microprocessors](/preview/png/542888.png)
A fast low power four-way set-associative translation lookaside buffer (TLB) is proposed. The proposed TLB allows single clock phase accesses at clock frequencies above 1 GHz. Comparisons to a conventional fully associative CAM tagged TLB, which is the type most commonly used in embedded processors, with the same number of entries on a 65 nm low standby power process show that the proposed design has 28% lower delay and up to 50% lower energy delay product. Unlike previous set-associative TLBs, which replicate the TLB to support multiple page sizes, multiple page sizes are supported on a way-by-way basis. Alternative conventional CAM tagged and set-associative TLBs are investigated with regard to access latency, power dissipation and hit rates.
Journal: Integration, the VLSI Journal - Volume 41, Issue 4, July 2008, Pages 509–523