Versatile hardware architectures for GF(pm)GF(pm) arithmetic in public key cryptography

In this paper new algorithms and versatile hardware architectures for generic computations of the type u=abp/cu=abp/c, u=bp/cu=bp/c and u=ab/cu=ab/c in the Galois field GF(pm)GF(pm) are described. In all cases the hardware operates independently of the defining irreducible polynomial of the field and the same hardware can be used for different field sizes offering full versatility up to a maximum field size. The performance of prototype implementations over Galois fields of characteristic p=3p=3 are discussed through FPGA implementation.