Design of a high-speed, low-noise CMOS data output buffer

The present paper describes the design of a very high-speed data output buffer in use at Intel Corporation's commercially available product. It utilizes several noise-suppression techniques for maximum noise reduction and describes the advantages as well as disadvantages of several other techniques currently in use at industry. It proposes architecture for pre-driver circuit, which mainly gave the buffer it's high-speed without raising the di/dt noise. Simulation results show that the speed of the buffer would be in between 2 and 7 ns while maintaining the derivative of output current within a range of ±50 and ±400 mA/ns with I/O supply voltages varying between 1.35 and 2.24 V.