کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
543071 1450481 2016 8 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
A background fast convergence algorithm for timing skew in time-interleaved ADCs
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
A background fast convergence algorithm for timing skew in time-interleaved ADCs
چکیده انگلیسی

Time-interleaved analog-to-digital converters (TI ADCs) suffer offset mismatch, gain mismatch, bandwidth mismatch and timing skew, of which timing skew degrades the performance most severely. In this paper, a background fast convergence calibration algorithm for timing skew is proposed. With known the range of input frequency, the algorithm employs the statistical property of the wrong digital outputs to estimate the sign of the timing skew. Then a correction module based on polynomial interpolation starts to compensate the wrong outputs. This algorithm has some merits of simplicity, fast convergence rate and feasible to implement. Behavioral simulation of an 8-bit 8-channel 3.2 GS/s TI ADC reveals that with an input frequency of 0–1.4 GHz, this algorithm is effective to improve the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the TI ADC.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 47, January 2016, Pages 45–52
نویسندگان
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