A background fast convergence algorithm for timing skew in time-interleaved ADCs

Time-interleaved analog-to-digital converters (TI ADCs) suffer offset mismatch, gain mismatch, bandwidth mismatch and timing skew, of which timing skew degrades the performance most severely. In this paper, a background fast convergence calibration algorithm for timing skew is proposed. With known the range of input frequency, the algorithm employs the statistical property of the wrong digital outputs to estimate the sign of the timing skew. Then a correction module based on polynomial interpolation starts to compensate the wrong outputs. This algorithm has some merits of simplicity, fast convergence rate and feasible to implement. Behavioral simulation of an 8-bit 8-channel 3.2 GS/s TI ADC reveals that with an input frequency of 0–1.4 GHz, this algorithm is effective to improve the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the TI ADC.