Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders

• Propose a general methodology for constructing hierarchical carry lookahead adders.
• Develop novel structures for hybrid ripple carry and hierarchical carry lookahead adders.
• Model system performance to estimate performance of different adder structures.
• Provide ASIC implementation for proposed and previously published designs.

This paper proposes improved structures for fast adders that include carry lookahead (CLA) and hierarchical carry lookahead (HCLA). Also, it proposes optimized novel structures of hybrid ripple carry/hierarchical carry lookahead (RCA/HCLA) adders. A general methodology is presented for constructing M-bit hierarchical carry lookahead adders using n-bit modules. The only restriction on the values of M or n   is n≤Mn≤M. Two algorithms are developed to efficiently construct hierarchical carry lookahead adders for the case when M is not an integer power or an integer multiple of n. The improved hierarchical levels of carry lookahead adders are integrated with the ripple carry adder to construct the novel hybrid RCA/HCLA adders. Area and time complexities of the resulting designs are reported for different values of radix n and the practical values of 32 and 64 bits of M. An ASIC implementation of the proposed structures and previously published recent designs shows that one of the proposed hybrid RCA/HCAL adders achieves 28.2–77.7% reduction in area–delay product and 40.5–75.8% reduction in energy, for M=64 and n=8, over the different compared adder designs.