A low power dissipation high-speed CMOS image sensor with column-parallel sigma–delta ADCs

• Two buffers are designed to provide power supply for inverters to improve the robustness.
• Due to the use of variable power supply, the sensitivity of inverter is reduced greatly.
• An inverter-based SC circuit is adopted to low-voltage low-power ΣΔ modulator.

A 60frames/s CMOS image sensor with column-parallel inverter-based sigma–delta (ΣΔ) ADCs is proposed in this paper. In order to improve the robustness of the inverter, instead of constant power supply, two buffers are designed to provide power supply for inverters. Instead of using of an operational amplifier, an inverter-based switch-capacitor (SC) circuit is adopted to low-voltage low-power ΣΔ modulator. Detailed analysis and design optimization are provided. Due to the use of the inverter-based ΣΔ ADCs, the conversion speed is improved while reducing the area and power consumption. The proposed CMOS image sensor has been fabricated with 0.18 μm CMOS process. The measurement results show that the random noise (RN) is 7erms−, the pixel conversion gain is 100 μV/e−. Since the measured full well capacity of the pixel is 25000e−, the CMOS image sensor achieves a 71 dB dynamic range (DR). The total power consumption at 60frame/s is 58.2 mW.