Co-design of multicore architectures and microfluidic cooling for 3D stacked ICs

In this paper, we investigate the co-design of multicore architectures and microfluidic cooling for 3D stacked ICs. The architecture is a 16 core, ×86 multicore die stacked with a second die hosting an L2 SRAM cache. First, a multicore ×86 compatible cycle-level microarchitecture simulator was constructed and integrated with physical power models. The simulator executes benchmark programs to create power traces that drive thermal analysis. Second, the thermal characteristics under liquid cooling were investigated using a compact thermal model. Four alternative packaging organizations were studied and compared. The greatest overall temperature reduction under a given pumping power is achieved, with two tiers and two pin fin enhanced microgaps, with the high power dissipation tier on the top. Third, an optimization of the pin fin parameters including the diameter, height, and longitudinal and transversal spacing was performed. This optimization is shown to achieve significant improvement in energy/instruction, and significant reductions in leakage power.