Timing characterization and constraining tool

This paper presents Timing Characterization and constraining Tool (TCT) that facilitates designing of modular reconfigurable Integrated Circuits (ICs) by supporting early constraint-based design space exploration and timing constraining. These steps of the design methodology are crucial from the perspective of quality of results and are not directly addressed by the synthesis tools used nowadays.Although the idea of TCT is presented here using one of the currently available logic synthesis tools as an example, it can be easily adapted for other ones. Such flexibility increase usability of TCT and makes it very helpful for scientists who look for new integrated architectures that utilize dynamically reconfigurable resources.