کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
543368 871657 2012 8 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
An all-digital DLL using novel harmonic-free and multi-bit SAR techniques
کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
An all-digital DLL using novel harmonic-free and multi-bit SAR techniques
چکیده انگلیسی

A novel Force/Release technique is proposed to eliminate the harmonic locking issue, which occurs in wide-range operation of Delay Locked Loops (DLLs). The proposed technique does not require replica delay line or multiphase clocks for frequency estimation, and hence, reduces the chip area and power consumption. Moreover, it can be employed, without modifications, to any type of the delay line controller. In addition, an area efficient technique for multi-bit Successive Approximation Register (SAR) DLL is proposed. A complete All-Digital DLL (ADDLL) design implementing the proposed Force/Release technique and the proposed 2-bit SAR scheme is developed. All design units are fully digital, described in Verilog and mapped to silicon using the IBM 0.13 μm Artisan standard cell library. The proposed design has an active area of 0.014 mm2 and can operate from 110 MHz to 1 GHz with a fixed latency of one clock cycle. It locks in 12 clock cycles and has a closed loop characteristics.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 43, Issue 6, June 2012, Pages 393–400
نویسندگان
, ,