A design methodology for integrated inductor-based DC–DC converters

A design methodology for monolithic integration of inductor based DC–DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 μm CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology.