کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
543660 871681 2009 10 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
A novel ADPLL design using successive approximation frequency control
کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
A novel ADPLL design using successive approximation frequency control
چکیده انگلیسی

This paper presents a hardware implementation of a fully synthesizable, technology-independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most eight reference cycles. ASICs in CMOS AMS 0.35μm and UMC 0.13μm have been manufactured and tested. Measurements show competitive results to state-of-the-art mixed-signal implementations.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 40, Issue 11, November 2009, Pages 1613–1622
نویسندگان
, , , , ,