Parallel links with current-mode incremental signaling and per-pin skew compensation

This paper proposes a new inter-signal timing skew compensation technique for parallel links with current-mode incremental signaling. Both the transmitter and receiver of the links are current-mode configured to utilize the intrinsic advantages of current-mode signaling. The receiver maps the direction of its channel currents representing the logic state of the incoming data to two voltages whose values are largely different, enabling a convenient recovery of both the logic state and timing information of the received current-mode data in the voltage-mode domain, and suppression of the common-mode disturbances coupled to the channels. Inter-signal timing skews are compensated by inserting a delay line in each channel whose time delay is determined by the phase difference between the transmitted master clock and the output of the recovering comparator. To assess the effectiveness of the proposed inter-signal timing skew compensation technique, a 2-bit 1 Gbytes/s parallel link has been designed in IBM-0.13μm1.2V CMOS technology and analyzed using SpectreRF with BSIM3V3 device models. Simulation results of the parallel link with the proposed deskewing scheme demonstrate that inter-signal timing skews can be effectively compensated using the proposed deskewing scheme.