Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors

• Some modifications inside the carry generation block of the CLAs have led to single error masking. This way, at most n simultaneous errors can be masked inside an n-bit CLA.
• The designed CLAs can detect multiple errors incurred by multiple faults with a high probability (about 90% in larger adders).
• Unlike TMR-based methods, the incorporated voters have been protected with no extra hardware overhead through a modified parity based fault detection.
• A low overhead architecture with satisfying correction/detection capabilities has been proposed.
• Verified by simulations it was analytically shown that these architectures have much more reliability than the others.

Currently, the demand for reliable and high performance computing is increasing due to the enlarging susceptibility of computing circuits to different environmental effects, and the advent of diverse computation-based applications. Arithmetic operators, as the main building blocks of the processing units in computing systems, are exposed to different types of single or multiple errors incurred by different faults which can seriously damage the whole system. In this paper, a new approach is presented to achieve fault-tolerant carry look-ahead adder architectures, much more efficient than the conventional methods, with the characteristic of robustness against multiple simultaneous errors. The proposed method is based on revising the carry generation block to achieve multiple error correction capability, and utilizing a modified parity prediction-based method that in combination with the proposed error correction scheme leads to multiple error detection capability. Verified by simulations, analytical assessments show that, as well as correcting or detecting all single permanent or transient errors, multiple simultaneous errors in the new carry look-ahead adders are corrected or at least detected with a high probability independent of the number of errors. Apart from having more reliability against multiple errors, these adders require lower area overheads compared to the state of the art designs as well as conventional fault-tolerant methods.