Degradation behavior of crystalline silicon solar cells in a cell-level potential-induced degradation test

The degradation behavior of crystalline silicon (c-Si) solar cells in a cell-level potential-induced degradation (PID) test and the effect of the test conditions are reported. The PID tests were performed in a vacuum chamber by applying a voltage of 1000 V from a temperature-controlled aluminum chuck underneath an unlaminated sample stack to the top copper electrode placed on the stack. The stack was composed of soda-lime glass, an ethylene vinyl-acetate copolymer sheet, and a conventional p-type c-Si solar cell. The investigated solar cell exhibited a large degradation of the fill factor and slight degradation of the open-circuit voltage. These degradations were mainly caused by a reduction in the parallel resistance, which is the same degradation behavior as that reported previously. This indicates that the cell-level PID test well reproduces the typical degradation behavior. However, the leakage current in the unlaminated sample stack at a relatively low temperature exhibited a different temperature dependence from that in a laminated sample stack. The difference in the temperature dependence was caused by temperature-dependent contact resistances within the unlaminated sample stacks. This indicates that there is a difference between the temperature dependences in cell-level and module-level PID tests. This difference in the temperature dependence was reduced by the use of a heavier top electrode. These findings may assist in choosing the proper test conditions for this kind of cell-level PID test. A cell-level PID test for an n-type front-emitter c-Si solar cell was also performed. A typical degradation behavior, characterized by reductions in the open-circuit voltage and the short-circuit current, was observed, which implies that this test can be widely applied to PID phenomena occurring in many kinds of solar cells.