Effects of low gate bias annealing in NBT stressed p-channel power VDMOSFETs

Effects of low gate bias annealing in NBT stressed p-channel power VDMOSFETs have been investigated to get better insight into the NBTI phenomena. Negative bias annealing does not affect stress-induced degradation significantly, whereas either zero or positive bias annealing removes the portion of stress-induced oxide-trapped charge while creating additional interface traps. The removable component of stress-induced oxide-trapped charge is found to decrease, and influence of external bias on annealing phenomena weakens with duration of preceding stressing, suggesting that extended stress moves the trapped charge to energetically deeper oxide traps, which are more difficult to anneal.