Extraction of 3D parasitic capacitances in 90 nm and 22 nm NAND flash memories

In this paper we propose to study different ways to extract the values of parasitic capacitances in 90 nm and 22 nm NAND Flash memories. Indeed, these parasitic capacitances between cells in the array can modify applied polarizations and can disturb the functioning of the whole array. Their impact increases when the cell size is reduced, especially as the ultimate size of the 22 nm node is reached. We develop 3D TCAD simulations to extract parasitic capacitances as well as measurements on specific test structures or geometrical calculations, showing their increasing importance in the future technologies, especially for 22 nm node.