A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation

Backend geometries on chips contain a wide variety of features. This paper analyzes data from test structures implemented on a 45 nm technology test chip to relate geometry to failure rate statistics. An area scaling model is constructed which accounts for the presence of die-to-die linewidth variation, and a methodology is proposed to account for die-to-die linewidth variation when determining if low-k materials satisfy lifetime requirements.