A dual-exposure wide dynamic range CMOS image sensor with 12 bit column-parallel incremental sigma-delta ADC

• 12-bit incremental sigma-delta ADC is developed to implement the synthesis of dual-exposure data on chip.
• The operational amplifier in ΣΔ modulator is replaced by a simple five-transistor single-stage amplifier.
• The use of ΣΔ ADC simplifiies the synthesis of long and short exposure images.

A wide dynamic range CMOS image sensor (CIS) based on the synthesis of long and short exposure signals is proposed. To achieve the high-speed readout, a high speed, 12-bit column-parallel incremental sigma-delta (ΣΔ) ADC including digital correlated double sampling (CDS) is developed to implement the synthesis of dual-exposure data on chip. Since the use of ΣΔADC, it does not require huge frame memory device to store conversion data, the synthesis of long and short exposure images simply and can be easily implemented on CIS chip, and the power dissipation is reduced. The CMOS image sensor has been fabricated with 0.18 μm 1P4M CIS process. This sensor achieves a dynamic range of 95 dB, and the measured results indicate that the random noise is 7erms−, the pixel conversion gain is 100 μV/e−, full well capacity of the pixel is 25000 e−, and the power dissipation of one ADC is only 32 μW.