Design guidelines for the integration of Geiger-mode avalanche diodes in standard CMOS technologies

The goal of this paper is to provide some useful design guidelines at the device level regarding the main challenges to be typically faced in the design and integration of Geiger-mode avalanche diodes in a standard CMOS process. Different techniques are found in literature in order to avoid premature edge breakdown with the aim of limiting the electric field at the edges to be weaker than in the multiplication region. In this article, the use of such techniques, the conditions where they can effectively work and above all their limitations are studied by means of TCAD simulations for various diode architectures. Additionally, the noise performance is discussed by focusing on the band-to-band tunneling and shallow trench isolation enhanced dark count rates. Geiger-mode bias techniques as well as a synthesis on the pros and cons of the various avalanche diode architectures are finally presented aiming at facilitating future design choices.