A scalable architecture for reducing power consumption in pipelined deep packet inspection system

A scalable architecture for reducing power consumption in pipelined AC-DFA (Aho-Corasick deterministic finite automaton) tries for deep packet inspection (DPI) system is proposed. A new scheme for deciding the strides of the AC-DFA trie is devised where the stride of each pipeline is decided variably to reduce the power consumption. Scaling down the clock frequency of the rarely-used stages is applied to reduce wasted power consumption. As a result, a DPI system with the proposed schemes shows a reduction of up to 27% in power consumption, compared with the state-of-the-art DPI systems.