A broadband Low Noise Amplifier with built-in linearizer in 0.13-µm CMOS process

A linearized ultra-wideband (UWB) CMOS Low Noise Amplifier (LNA) is presented in this paper. The linearity performance is enhanced by exploiting PMOS–NMOS common-gate (CG) inverter as a built-in linearizer which leads to cancel out both the second- and third-order distortions. Two inductors are placed at the drain terminals of CG transistors in the built-in linearizer to adjust the phase and magnitude of the third-order distortion. A second-order band-pass Chebyshev filter is utilized in the input port of common-source (CS) configuration to provide broadband input matching at 3.1–10.6 GHz frequency range to a 50-Ω antenna. Series and shunt peaking techniques are employed to extend the bandwidth (BW) and to flatten the gain response. Simulated in 0.13 µm CMOS technology, the CMOS LNA exhibits state of the art performance consuming 17.92 mW of dc power. The CMOS LNA features a maximum gain of 10.24 dB, 0.9–4.1 dB noise figure (NF), and a third-order input intercept point (IIP3) of 6.8 dBm at 6.3 GHz.