A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications

• Mathematical formulations are derived to aid in the circuit design.
• The transient response of the LDO is enhanced by a pair of CMFB resistors.
• The LDO is able to settle within 2 µs while consuming 4.45 µA of quiescent current.

In this paper, a highly efficient and fast transient output capacitor-free low-dropout regulator (LDO) presented. The proposed LDO architecture is based on differential transconductance amplifiers pairing with push–pull stage to enable effective output driving capability. The slew rate at the gate of the output transistor (SRG)(SRG) is further enhanced by common mode-feedback (CMFB) resistors and a coupling capacitor to bypass band-limited components. By adopting adaptive biasing (ADB) technique, the loop bandwidth is extended proportionally to the output load while maintaining high current efficiency at minimum load. The proposed LDO is designed using cost-effective 0.35 µm CMOS technology. Post-layout simulation results show that the LDO occupies an active area of 0.069 mm2, consuming only a quiescent current of 4.45 µA at a minimum load of 100 µA. The LDO is able to regulate the output at constant 1.2 V with a dropout voltage of 0.2 V. When the load is ramped from 100 µA to 100 mA in 100 ns, the output transient can be fully recovered within 2 µs.

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