Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10 GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65 nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1 dBc/Hz and power consumption 3.71 mW at the operating frequency 5.2 GHz under supply voltage 1.4 V. The second chip of proposed VCO can achieve power consumption Sub 1 mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082 GHz to 5.958 GHz with tuning range of 15.8%. The measured phase noise is −115.88 dBc/Hz at 1 MHz offset at the operation frequency of 5.815 GHz. and the dc core current consumption is 0.71 mA at a supply voltage of 1.4 V. Its figure of merit (FOM) is −191 dBc/Hz. Two circuits were taped out by TSMC 0.18 μm 1P6M process.