An FPGA based scalable architecture of a stochastic state point process filter (SSPPF) to track the nonlinear dynamics underlying neural spiking

Recent studies have verified the efficiency of stochastic state point process filter (SSPPF) in coefficients tracking in the modeling of the mammalian nervous system. In this study, a hardware architecture of SSPPF is both designed and implemented on a field-programmable gate array (FPGA). It provides a time-efficient method to investigate the nonlinear neural dynamics through coefficients tracking of a generalized Laguerre–Volterra model describing the spike train transformations of different brain sub-regions. The proposed architecture is able to process matrices and vectors with arbitrary sizes. It is designed to be scalable in parallel degree and to provide different customizable levels of parallelism, by exploring the intrinsic parallelism of the FPGA. Multiple architectures with different degrees of parallelism are explored. This design maintains numerical precision and the proposed parallel architectures for coefficients estimation are also much more power efficient.