QBNoC: QoS-aware bufferless NoC architecture

Chip area and power consumption are the main restrictions for Network-on-Chip (NoC), a high proportion of which is consumed by the buffers in the routers. Therefore, bufferless NoC, which completely eliminates in-router buffers, has been proposed. However, the existing bufferless NoC designs do not provide Quality-of-Service (QoS) guarantee. In this paper, we propose a QoS-aware Bufferless NoC, named QBNoC. QBNoC employs hybrid switching mechanism, namely circuit switching mechanism for real-time application and wormhole switching mechanism for other applications. Besides, in order to decrease the deflection probability and thus improve the performance of the network, we propose a new output port allocation policy, named Two-Stage Allocation (TSA). Furthermore, new router architecture with shorter critical path is designed for QBNoC. The evaluation results show that by efficiently exploiting resources, our proposal significantly improves the performance of the whole network, and meanwhile satisfies the QoS requirements of different applications.