Extraction of scalable electrical model for a SOI JFET using BSIM3 model

It is well known that junction field effect transistor (JFET) has excellent behaviors in terms of low frequency noise (flicker noise). For this reason, it is used for all applications where noise must be as lower as possible and very high input impedance is needed.A JFET has been designed and realized in a BCD SOI technology and fully characterized in terms of DC, AC and noise measurements.To achieve an accurate modeling of the experimental data for circuit simulations, an evaluation of Schichman and Hodges JFET models has been carried out. However, basic limitations have been detected because subthreshold current is not described and model parameters are too few to properly fit the experimental data both in linear and saturation regions. Therefore it has been decided to carry study on modeling starting from the BSIM3 model equations.

► n-channel junction field effect transistor has been realized in a SOI technology.
► Different models have been explored to obtain a good accuracy in all operating regions.
► Unconventional model approach has been experimented (BSIM3).
► A very precise and scalable model has been obtained.