A 1.2 V, 130 nm CMOS parallel continuous-time ΣΔΣΔ ADC for OFDM UWB receivers

The design and implementation in a 1.2 V, 130 nm CMOS technology of a parallel continuous-time ΣΔΣΔ modulator for OFDM UWB signals is described. Once the parallel architecture and the metrics used are presented, the NTF is optimized and implemented using a third order lowpass and a fourth order bandpass modulator. Both are CRFB structures which use active-RC integrators. Then, the circuital blocks are discussed and some comments about the test set-up are given. Experimental results show good agreement with both system-level and layout-level simulations, with up to 15 dB DR for QPSK modulation over a signal bandwidth of 528 MHz, with a 62.3 mW power consumption.