کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
546377 | 871897 | 2010 | 6 صفحه PDF | دانلود رایگان |
This paper presents the design optimization of fully pipelined architectures for area-time-power-efficient implementation of finite impulse response (FIR) filter. The architectures are designed to obtain a suitable area-time tradeoff. Analysis of the performance of different filter orders and different address lengths of partial tables indicate the choice of four input partial tables presents the best of area-time-power-efficient realizations of FIR filter compared with the existing LUT-less DA-based implementations of FIR filters in both high-speed and medium-speed. Moreover, a number of further experiments not only shows the pipeline register’s significant influence to the maximum frequency of the FIR filters but also indicates it also has area usage. Final experiment shows that with the help of using pipeline register, the choice of 4-bits-per-clock (4BPC) of the architecture for word-length N=8 with four input partial table yields the best cost-effective when comparing with other different cases in both high-speed and medium-speed implementations.
Journal: Microelectronics Journal - Volume 41, Issue 6, June 2010, Pages 365–370