Self-tuning adaptive delay sequential elements

Random manufacturing variations and changes in operating conditions can alter the relative timing of data and clock signals and cause timing violations. Increasing relative magnitude of manufacturing variations and accommodating a wide range of operating conditions necessitate large design margins and decrease circuit performance. In-circuit tuning of clock latencies allows recovering some of the performance loss. In this paper, we introduce self-tuning adaptive-delay sequential elements (SASEs) that use PMOS floating gates to tune clock latencies of individual flip-flops. SASEs are capable of concurrent, in-circuit optimization of clock latencies under varying operating conditions. We use examples of implicit and explicit pulsed flip-flops to present SASEs operations and tuning methods. Our experiments with fabricated prototypes show that SASEs can tune their clock latencies with picosecond resolution over one half of the clock period. Our experiments also show that SASEs’ sensitivities are comparable to non-adaptive flip-flops and do not pose any practical limitations. We also present a tuning procedure for pipeline circuits that tunes SASEs’ clock latencies to maximize performance.