کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
546729 | 871937 | 2006 | 11 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems](/preview/png/546729.png)
چکیده انگلیسی
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts of applications on coarse-grain reconfigurable hardware. The reconfigurable hardware blocks are embedded in a heterogeneous reconfigurable system architecture. The fine-grain part is implemented by an embedded FPGA unit, while for the coarse-grain reconfigurable hardware our developed high-performance coarse-grain data-path is used. The design flow mainly consists of three steps; the analysis procedure, the mapping onto coarse-grain blocks, and the mapping onto the fine-grain hardware. In this work, the methodology is validated using five real-life applications; an OFDM transmitter, a medical imaging technique, a wavelet-based image compressor, a video compression scheme and a JPEG encoder. The experimental results show that the speedup, relative to an all-FPGA solution, ranges from 1.55 to 4.17 for the considered applications.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 37, Issue 6, June 2006, Pages 554-564
Journal: Microelectronics Journal - Volume 37, Issue 6, June 2006, Pages 554-564
نویسندگان
Michalis D. Galanis, Athanassios Milidonis, Athanassios P. Kakarountas, Costas E. Goutis,