Elimination of stress induced dislocation in deep Poly Sinker LDMOS technology

• The relationship between leakage current and dislocation shown in Poly Sinker LDMOS is studied.
• Distribution of the dislocation is investigated and a stress-induced dislocation (SID) model is proposed.
• The SID model is verified by measuring wafer warpage change at each key step.
• Two methods are proposed and proven to eliminate dislocation and the stress-induced leakage current effectively.

This work investigates the leakage current of power LDMOS (laterally diffused metal–oxide–semiconductor) transistors with deep poly sinker, and the leakage shows a certain wafer map distribution with most of the failed dies located at the center area. It is found that the leakage current is mainly caused by the stress-induced dislocations close to the deep poly sinker. The relationship between the stress-induced dislocation (SID) and the wafer warpage is studied. Experimental results show the dislocation and the resulting leakage current can be effectively eliminated, by either modifying the device layout or optimizing the fabrication process of the poly sinker.