Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method

• We apply PTM approach and enrich its ability to analyze CED circuit under multiple faults.
• A fault model is proposed based on the relevance of input pattern and the gate topology.
• Different aspects of CED schemes are evaluated under identical and diverse failure rates of transistors.
• The impact of transistors to circuit reliability with respect to fault masking property is explored.

Transient faults are important concerns in emerging ICs built from deep semiconductors. Concurrent error detection (CED) scheme has been proved to be an efficient technique in such a context. On the other hand, the increase of multiple faults can be foreseeable in future ICs. However, reported efforts applied to quantify the efficiency of CED schemes mostly consider single faults or suppose that implemented checker mechanisms are fault-free. This paper describes an alternative analytical solution for CED circuits analysis under a more realistic hypothesis. In addition to the assumption of the whole fault-prone circuit (including checker mechanisms), different failure rates of logic gate are considered as well. The proposed approach is based on probabilistic transfer matrices and then can deal with multiple faults. The time efficiency of the proposed solution is demonstrated through arithmetic circuits. By applying this solution, classical CED schemes are discussed according to different failure rates of transistor.