An asynchronous 12-bit 50 MS/s rail-to-rail Pipeline-SAR ADC in 0.18 μm CMOS

This paper presents a 12-bit 50 MS/s asynchronous rail-to-rail Pipeline-SAR ADC. Design optimization is performed to achieve low power and high performance. The ADC consists of a 6-bit coarse SAR ADC, a residue amplifier and a 7-bit fine SAR ADC. A novel highly linear, power efficient switching scheme for the 2nd stage SAR ADC is proposed. The ADC operates asynchronously in order to simplify the design and save power. The ADC achieves low-power, high-resolution and high-speed operation without calibration. The ADC was fabricated in 0.18 μm CMOS process with 1.8 V power supply range. The proposed SAR ADC achieves 67.01 dB SNDR and 77.13 dB SFDR with sampling rate up to 50 MS/s, corresponding to a figure-of-merit of 110 fJ/conversion-step. The proposed ADC core occupies an active area of about 450×700 µm2.