High speed multiplexer design using tree based decomposition algorithm

• This paper proposes an efficient high speed (less delay) digital multiplexer design.
• Number of possible cases for multiplexer using proposed method is less than existing.
• The same proposed method can be used for an area efficient multiplexer design.
• The multiplexers using proposed method are synthesized and compared with existing.
• The synthesis results show that the proposed method gives the good designs.

This paper proposes an effective algorithm to design a larger multiplexer using a tree of smaller multiplexers for a particular user defined library. The proposed algorithm outputs the larger multiplexer into a tree based structure, which gives the scope to pipeline the larger multiplexer as per the requirements of data path design. The experimental result shows that the proposed algorithm gives an efficient multiplexer design with less delay compared to existing algorithms. For example, 48-to-1, 31-to-1 multiplexer designs using the proposed algorithm achieve an improvement of 30.4% and 21.95% in delay compared with designs using 2-to-1 multiplexer tree for 45nm technology respectively.