A two-level approximate model driven framework for characterizing Multi-Cell Upsets impacts on processors

• Constructing an approximately mapped PGM model for SBU estimation.
• Decomposing MCU issue into SBUs via a histogram analysis based boundary model.
• Achieving 15.37× speedup while only 8.17% accuracy loss for complex MCU estimation.

Soft error analysis is very significant for a good tradeoff between processor design cost (e.g. area and power) and reliability. In this paper, we propose an approximate model driven framework for efficient soft error analysis in processors. The proposed framework includes: 1) an approximate Probabilistic Graphical Model (PGM) for the Single Bit Upset (SBU) estimation, uses average-and-max policy to handle the mapped PGM structure, node parameter and inference fast; 2) an approximate boundary model for the more complex Multi-Cell Upsets (MCU) case, adopts relax-and-strict way to reuse the approximate PGM model and characterize MCU patterns completely. The comprehensive results confirm that, compared with the state-of-the-art, the proposed two-level methodology based on approximate models achieves fast estimation up to more 15.37× speedup while only 8.14% accuracy loss on average. Furthermore, the complex MCU impacts are also estimated by the proposed method at the same order of magnitude as the runtime of the simple SBU case.