Adaptive refresh structure for gain cell embedded DRAM

• Used a replica row to trace the PVT and the same write disturbance as the data array.
• Proposed an adaptive detection period method to reduce the detection frequency.
• An adjustable WWL voltage is used for replica row for post-silicon calibration.

Recently, gain cell eDRAMs have been attractive alternatives to SRAM and 1T1C DRAM for high density and logic-compatible embedded memories. The refresh period is traditionally determined according to the highest working temperature and worst-case access statistics, which results in a short refresh period and large refresh power. In this paper, an adaptive refresh structure is proposed to increase the refresh period and reduce the refresh power for gain cell eDRAMs in space application. A replica row of weak gain cells is inserted into the gain cell eDRAM bank to trace the chip temperature and access statistics and it is checked periodically to control the refresh period adaptively. A gain cell eDRAM bank of 256×256 with the structure is designed and simulated in SMIC 130 nm logic process. Simulation results show the proposed structure traces chip temperature and access statistics efficiently and closely, and it reduces the refresh power by about 95.2% compared with traditional fixed period design.