Analysis and design of a two-stage amplifier with enhanced performance

A high gain two-stage amplifier is presented in this paper, with detailed theoretical analysis. The proposed topology employs positive resistive-capacitive feedback to introduce an extra left half plane zero to cancel a non-dominant pole at the output of the first stage. Since the dominant pole is at the output of the amplifier, stability of the amplifier will not be sensitive to load variations. The proposed amplifier is designed in a 0.18 µm complementary metal-oxide-semiconductor process with a core area of 2597 µm2. The amplifier dissipates 0.896 mW from a 1.8 V power supply. Also, DC gain, gain bandwidth (GBW), phase margin and slew rate for a 10 pF capacitive load are 79.5 dB, 93.6 MHz, 66.9° and 18.2 V/µS, respectively. Moreover, the proposed amplifier topology and the adopted compensation scheme provide 35.3 dB for common-mode rejection ratio and 27.1 dB for positive power supply rejection ratio at GBW frequency. For 1% and 0.1% accuracy, settling times of the proposed two-stage amplifier are 31.2 and 47.3 ns for 0.5 V input signal and 10 pF capacitive load. Simulation results confirm convenient performance of the circuit at all process corners, in the presence of a mismatch, power supply noise and input common mode variations.